The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jun. 07, 2016

Filed:

May. 04, 2015
Applicants:

Ateet Omer, Kanpur, IN;

Deependra K. Jain, Noida, IN;

Anand Kumar Sinha, Noida, IN;

Krishna Thakur, Noida, IN;

Inventors:

Ateet Omer, Kanpur, IN;

Deependra K. Jain, Noida, IN;

Anand Kumar Sinha, Noida, IN;

Krishna Thakur, Noida, IN;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H03K 3/00 (2006.01); H03K 3/012 (2006.01); H03K 5/24 (2006.01); H03K 5/156 (2006.01);
U.S. Cl.
CPC ...
H03K 3/012 (2013.01); H03K 5/1565 (2013.01); H03K 5/24 (2013.01);
Abstract

A clock generator includes a diagnostic circuit that includes first and second muxes, first and second comparators, a logic gate, and a counter. The first mux receives first and second voltage signals and outputs a first intermediate signal based on a control signal. The second mux receives third and fourth voltage signals and outputs a second intermediate signal based on the control signal. The first and second comparators compare the intermediate signals with a first signal that is indicative of a DC value of the clock signal for generating first and second comparison signals. The logic gate receives the first and second intermediate signals and generates a control signal. The counter receives the clock signal and the control signal and generates a clock ready signal that is indicative of stability and quality of the clock signal.


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