The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jun. 07, 2016

Filed:

Oct. 26, 2012
Applicant:

Fuji Electric Co., Ltd., Kawasaki-shi, JP;

Inventor:

Koji Sasaki, Matsumoto, JP;

Assignee:

FUJI ELECTRIC CO., LTD., Kawasaki-shi, JP;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 29/732 (2006.01); H01L 29/417 (2006.01); H01L 23/48 (2006.01); H01L 29/66 (2006.01); H01L 29/739 (2006.01); H01L 29/06 (2006.01);
U.S. Cl.
CPC ...
H01L 29/41708 (2013.01); H01L 23/481 (2013.01); H01L 29/0696 (2013.01); H01L 29/66348 (2013.01); H01L 29/7397 (2013.01);
Abstract

A semiconductor device includes a semiconductor substrate which functions as an ndrift layer, a trench IGBT formed in the front surface, an interlayer insulator film, and a metal electrode layer on the interlayer insulator film. There is a contact hole in the interlayer insulating film which has a first opening formed on the metal electrode layer side and a second opening on the semiconductor substrate side. Width wof the first opening on the metal electrode layer side is wider than width wof first opening on the semiconductor substrate side, in a direction perpendicular to the extending direction of the trench in the planar pattern of trenches. The metal electrode layer is connected to a p-type channel region and an nsource region via the contact hole. The method of manufacturing improves the reliability of the device.


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