The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jun. 07, 2016

Filed:

Jul. 19, 2012
Applicants:

Seung-eon Ahn, Hwaseong-si, KR;

I-hun Song, Hwaseong-si, KR;

Sang-hun Jeon, Seoul, KR;

Young Kim, Yongin-si, KR;

Yong-woo Jeon, Seoul, KR;

Chang-jung Kim, Yongin-si, KR;

Inventors:

Seung-eon Ahn, Hwaseong-si, KR;

I-hun Song, Hwaseong-si, KR;

Sang-hun Jeon, Seoul, KR;

Young Kim, Yongin-si, KR;

Yong-woo Jeon, Seoul, KR;

Chang-jung Kim, Yongin-si, KR;

Assignee:
Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 27/146 (2006.01); G06F 3/041 (2006.01); G06F 3/042 (2006.01);
U.S. Cl.
CPC ...
H01L 27/14609 (2013.01); G06F 3/0412 (2013.01); G06F 3/0421 (2013.01); G06F 2203/04103 (2013.01);
Abstract

In one embodiment, a light-sensing apparatus includes a light-sensing pixel array that has a plurality of light-sensing pixels arranged in rows and columns; and a gate driver configured to provide the light-sensing pixels with a gate voltage and a reset signal that have inverted phases. Each of the light-sensing pixels includes a light sensor transistor configured to sense light and a switch transistor configured to output a light-sensing signal from the light-sensor transistor. The gate driver includes a plurality of gate lines connected to gates of the switch transistors, a plurality of reset lines connected to gates of the light sensor transistors, and a plurality of phase inverters each connected between a corresponding reset line and a gate line. Thus, when a gate voltage is applied to one of the plurality of gate lines, a reset signal with an inversed phase to the gate voltage may be applied to a corresponding reset line.


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