The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jun. 07, 2016

Filed:

Aug. 18, 2015
Applicant:

Renesas Electronics Corporation, Koutou-ku, Tokyo, JP;

Inventors:

Takaomi Nishi, Tokyo, JP;

Takehiko Saito, Tokyo, JP;

Katsuhiro Torii, Tokyo, JP;

Assignee:
Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 21/44 (2006.01); H01L 23/00 (2006.01); H01L 23/528 (2006.01); H01L 23/532 (2006.01);
U.S. Cl.
CPC ...
H01L 24/03 (2013.01); H01L 23/528 (2013.01); H01L 23/53228 (2013.01); H01L 24/11 (2013.01); H01L 2224/0381 (2013.01); H01L 2224/03464 (2013.01); H01L 2224/03828 (2013.01); H01L 2224/03849 (2013.01); H01L 2224/0401 (2013.01); H01L 2224/05082 (2013.01); H01L 2224/05144 (2013.01); H01L 2224/05155 (2013.01); H01L 2224/1181 (2013.01); H01L 2224/11849 (2013.01); H01L 2924/01024 (2013.01);
Abstract

A manufacturing method for semiconductor devices includes the steps of forming an Ni/Au film that includes an Ni film and an Au film formed over the Ni film over a wiring that is coupled to each of a plurality of electrode pads formed over a principal surface of a semiconductor wafer and arranges each of the electrode pads at a different position, grinding a back surface of the semiconductor wafer, performing reduction treatment on a surface of the Ni/Au film, and forming a solder bump over the Ni/Au film. In the reduction treatment, respective processes of flux application, reflow soldering and cleaning are performed and the solder bump is bonded to the Ni/Au film after the reduction treatment has been completed. Thereby, bonding reliability in flip chip bonding of a semiconductor device is improved.


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