The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jun. 07, 2016

Filed:

Jun. 19, 2013
Applicant:

Stmicroelectronics S.r.l., Agrate Brianza, IT;

Inventors:

Agatino Minotti, Mascalucia, IT;

Maurizio Maria Ferrara, Catania, IT;

Assignee:

STMicroelectronics S.r.l., Agrate Brianza, IT;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/00 (2006.01); H01L 21/56 (2006.01); H01L 23/14 (2006.01); H01L 23/538 (2006.01); H01L 21/78 (2006.01); H01L 23/498 (2006.01); H01L 21/02 (2006.01);
U.S. Cl.
CPC ...
H01L 21/56 (2013.01); H01L 21/78 (2013.01); H01L 23/142 (2013.01); H01L 23/49827 (2013.01); H01L 23/5389 (2013.01); H01L 21/02107 (2013.01); H01L 21/02109 (2013.01); H01L 21/02225 (2013.01); H01L 21/02318 (2013.01); H01L 2924/0002 (2013.01);
Abstract

A method for making a set of electronic devices is proposed. The method comprises the steps of providing a support comprising a base plate of electrically conductive material, fixing a set of chips of semiconductor material onto respective portions of the base plate, each chip having a first main surface with at least one first conduction terminal and a second main surface opposite the first main surface with at least one second conduction terminal electrically connected to the base plate, fixing an insulating tape of electrically insulating material comprising a plurality of through-holes to the main surface of each chip, the insulating tape protruding from the chips over a further portion of the base plate being not covered by the chips, and forming at least one first electrical contact to each first terminal of the chips through a first set of the through-holes exposing at least in part said first terminal, and at least one second electrical contact to the base plate through a second set of the through-holes exposing at least in part the further portion of the base plate.


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