The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jun. 07, 2016

Filed:

Sep. 16, 2014
Applicant:

SK Hynix Inc., Gyeonggi-do, KR;

Inventor:

Young-Bo Shim, Gyeonggi-do, KR;

Assignee:

SK Hynix Inc., Gyeonggi-do, KR;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G11C 17/00 (2006.01); G11C 29/12 (2006.01); G11C 7/20 (2006.01); G11C 29/00 (2006.01); G11C 7/10 (2006.01); G11C 17/16 (2006.01); G11C 17/18 (2006.01); G11C 7/22 (2006.01); G11C 11/16 (2006.01); G11C 13/00 (2006.01); G11C 16/00 (2006.01); G11C 16/12 (2006.01); G11C 17/14 (2006.01); G11C 29/04 (2006.01); G11C 29/44 (2006.01);
U.S. Cl.
CPC ...
G11C 29/1201 (2013.01); G11C 7/1006 (2013.01); G11C 7/1051 (2013.01); G11C 7/1072 (2013.01); G11C 7/1078 (2013.01); G11C 7/20 (2013.01); G11C 7/22 (2013.01); G11C 17/16 (2013.01); G11C 17/18 (2013.01); G11C 29/70 (2013.01); G11C 11/16 (2013.01); G11C 13/00 (2013.01); G11C 16/00 (2013.01); G11C 16/12 (2013.01); G11C 17/143 (2013.01); G11C 2029/0407 (2013.01); G11C 2029/4402 (2013.01);
Abstract

A semiconductor device includes a nonvolatile memory block suitable for outputting data stored in a plurality of nonvolatile memory cells included therein based on first control information, and programming data in the nonvolatile memory cells based on second control information; a control block suitable for generating the first control information based on an initialization signal, wherein the control block sequentially generates the second control information and the first control information when a program mode is activated; and a test control block suitable for deactivating the nonvolatile memory block and determining whether at least one control signal among a plurality of control signals included in the first and second control information is normally generated, in a test operation on the program mode.


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