Memory addressing mechanism using a buffer of a hierarchy of collision free hash tables

Abstract

Methods and apparatuses for insertion, searching, deletion, and load balancing using a hierarchical series of hash tables are described herein. The techniques disclosed provide nearly collision free or deterministic hash functions using a bitmap as a pre-filter. The hash functions have different priorities and one hashing result will be used to perform main memory access. For the hash functions, two hash bitmaps are used to store valid data and collision information. There is no collision allowed in the hash tables except for the hash table with the lowest priority. The hash tables and bitmaps may be stored in one or more caches in (e.g., a cache of a CPU, Block RAMs in FPGAs, etc.) which perform much faster than main memory.