The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jun. 07, 2016

Filed:

Nov. 06, 2014
Applicant:

Em Microelectronic-marin SA, Marin, CH;

Inventors:

Nicolas Pillin, St-Sulpice, CH;

Goran Stojanovic, Neuchatel, CH;

Tony Ghueldre, Montignac, FR;

Assignee:
Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G06K 19/06 (2006.01); G01R 19/04 (2006.01); G06K 7/00 (2006.01); H03D 1/10 (2006.01); H03D 1/18 (2006.01); H04L 27/06 (2006.01); G06K 19/07 (2006.01);
U.S. Cl.
CPC ...
G01R 19/04 (2013.01); G06K 7/0008 (2013.01); G06K 19/07 (2013.01); G06K 19/0713 (2013.01); H03D 1/10 (2013.01); H03D 1/18 (2013.01); H04L 27/06 (2013.01); H03D 2200/0011 (2013.01); H03D 2200/0043 (2013.01); H03D 2200/0098 (2013.01);
Abstract

An envelope detector circuit, suitable for use in RFID tags, includes a voltage doubler circuit and a biasing voltage generating circuit which comprises components matched respectively to rectifying components of the voltage doubler circuit. A rectifying component of this voltage doubler circuit is formed by a transistor controlled by the biasing voltage generating circuit which provides a biasing voltage to a control gate of this transistor, the biasing voltage generating circuit being arranged so as to permit a determined forward biasing current to flow through the transistor and further rectifying elements of the voltage doubler circuit. This embodiment provides fast, highly sensitive detection of envelope waveforms in input signals. Thanks to the matched rectifying components, efficiency variations due to variations in manufacturing process can be eliminated. The envelope detector circuit is further arranged for maintaining a stable detection independent of variations in temperature.


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