The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
May. 31, 2016

Filed:

Jul. 02, 2015
Applicant:

Morgan / Weiss Technologies Inc., Beaverton, OR (US);

Inventors:

Morgan Johnson, Portland, OR (US);

Frederick G. Weiss, Newberg, OR (US);

Assignee:

Morgan/Weiss Technologies Inc., Beaverton, OR (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H05K 1/11 (2006.01); G06F 1/32 (2006.01); H05K 1/02 (2006.01); H01L 23/32 (2006.01); H05K 1/14 (2006.01); H05K 1/18 (2006.01);
U.S. Cl.
CPC ...
H05K 1/115 (2013.01); G06F 1/32 (2013.01); H01L 23/32 (2013.01); H05K 1/0237 (2013.01); H05K 1/0243 (2013.01); H05K 1/111 (2013.01); H05K 1/147 (2013.01); H01L 2924/0002 (2013.01); H05K 1/141 (2013.01); H05K 1/189 (2013.01); H05K 2201/095 (2013.01); H05K 2201/10159 (2013.01); H05K 2201/10189 (2013.01); H05K 2201/10378 (2013.01); H05K 2201/10515 (2013.01); Y10T 29/4913 (2015.01);
Abstract

A multi-layer interposer substrate includes multiple layers of single interposer substrates. Each single interposer substrate has a first array of interposer interconnects, each interposer interconnect in the first array of interposer interconnects corresponding to interconnects in an array of processor interconnects, a second array of interposer interconnects, each interposer interconnect in the second array of the interposer interconnects corresponding to an array of circuit interconnects on a circuit substrate, and at least one conductive trace in the interposer substrate in connection with at least one interconnect in the first array of interposer interconnects. The conductive trace has a parallel portion parallel to the interposer substrate such that no electrical connection exists between the interconnect and a corresponding one of the interposer interconnects in the second array of interposer interconnects. An array of connections for a peripheral circuit on each single interposer is connected to the at least one conductive trace.


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