The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
May. 31, 2016

Filed:

Feb. 20, 2013
Applicant:

Sony Corporation, Tokyo, JP;

Inventors:

Yuusuke Nishida, Fukuoka, JP;

Yasuaki Hisamatsu, Kanagawa, JP;

Assignee:

SONY CORPORATION, Tokyo, JP;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H04N 5/335 (2011.01); H04N 5/3745 (2011.01); H03K 4/08 (2006.01); H03K 21/02 (2006.01); H03M 1/00 (2006.01); H03M 1/06 (2006.01); H03M 1/12 (2006.01); H04N 5/378 (2011.01); H03M 1/08 (2006.01); H04N 5/357 (2011.01); H03M 1/56 (2006.01);
U.S. Cl.
CPC ...
H04N 5/37455 (2013.01); H03K 4/08 (2013.01); H03K 21/023 (2013.01); H03M 1/002 (2013.01); H03M 1/0617 (2013.01); H03M 1/0845 (2013.01); H03M 1/12 (2013.01); H04N 5/3577 (2013.01); H04N 5/378 (2013.01); H03M 1/123 (2013.01); H03M 1/56 (2013.01);
Abstract

The present invention relates to a column A/D converter, column A/D conversion method, imaging device, and camera system that can reduce the amount of IR drop by dispersing the current consumed during the count operation, mitigate the counter characteristic degradation, readily reduce the amount of fluctuation in the power source voltage, and achieve operation at a low power source voltage. The column A/D converter includes a plurality of column processing units including an A/D conversion function, a plurality of counters configured to generate digital codes in response to a reference clock and arranged corresponding to each or a set of the column processing units, and a count start offset unit configured to trigger a pseudo count operation in each of the counters and to offset a count start code for at least two or more counters among the plurality of counters before the reference clock is supplied to the counters.


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