The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
May. 31, 2016
Filed:
Jul. 06, 2015
Sarma Vrudhula, Chandler, AZ (US);
Jinghua Yang, Tempe, AZ (US);
Niranjan Kulkarni, Phoenix, AZ (US);
Shimeng Yu, Tempe, AZ (US);
Sarma Vrudhula, Chandler, AZ (US);
Jinghua Yang, Tempe, AZ (US);
Niranjan Kulkarni, Phoenix, AZ (US);
Shimeng Yu, Tempe, AZ (US);
Arizona Board of Regents on Behalf of Arizona State University, Scottsdale, AZ (US);
Abstract
This disclosure relates generally to threshold logic elements for integrated circuits (ICs). In one embodiment, a threshold logic element has a first input gate network, a second input gate network, a differential sense amplifier, and a resistive network. The first input gate network is configured to receive a first set of logical signals, while the second input gate network configured to receive a second set of logical signals. The differential sense amplifier is operably associated with the first input gate network and the second input gate network such that the differential sense amplifier is configured to generate a differential output in accordance with a threshold logic function. The resistive network is coupled between the differential sense amplifier and the first input gate network and between the differential sense amplifier and the second input gate network. The resistive network makes the threshold logic element less susceptible to process variations.