The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
May. 31, 2016

Filed:

Jul. 07, 2014
Applicant:

Huawei Technologies Co., Ltd., Shenzhen, Guangdong, CN;

Inventors:

Ming Li, Shenzhen, CN;

Jianping Wang, Chengdu, CN;

Caofei Heng, Chengdu, CN;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H02M 1/36 (2007.01); H02M 3/158 (2006.01); H02M 1/08 (2006.01); H03K 17/06 (2006.01);
U.S. Cl.
CPC ...
H02M 3/158 (2013.01); H02M 1/08 (2013.01); H03K 17/063 (2013.01); H03K 2217/0081 (2013.01);
Abstract

Embodiments of the present invention disclose a power supply conversion apparatus, where a control unit generates a corresponding control signal according to a received high level pulse width modulation signal, to control a first PMOS transistor Q, a second PMOS transistor Q, and a second NMOS transistor Qto be turned off successively, and then to make a first NMOS transistor Qconducted, which makes a voltage at a second end of a bootstrap capacitor to rise from ground potential to a PVDD, so that a voltage at a first end of the bootstrap capacitor rises to a PVDD+AVDD as the voltage at the second end rises, and a gate turn-on voltage of the first NMOS transistor Qreaches the PVDD+AVDD.


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