The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
May. 31, 2016
Filed:
May. 07, 2015
Applicant:
Yunhyeok Im, Hwaseong-si, KR;
Inventor:
Yunhyeok Im, Hwaseong-si, KR;
Assignee:
SAMSUNG ELECTRONICS CO., LTD., Suwon-si, Gyeonggi-do, KR;
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 23/02 (2006.01); H01L 25/065 (2006.01); H01L 23/495 (2006.01); H01L 23/00 (2006.01); H01L 23/31 (2006.01); H01L 23/373 (2006.01); H01L 23/498 (2006.01); H01L 25/10 (2006.01);
U.S. Cl.
CPC ...
H01L 25/0657 (2013.01); H01L 23/3128 (2013.01); H01L 23/3737 (2013.01); H01L 23/49541 (2013.01); H01L 23/49816 (2013.01); H01L 24/17 (2013.01); H01L 25/105 (2013.01); H01L 23/49568 (2013.01); H01L 2224/16057 (2013.01); H01L 2224/16245 (2013.01); H01L 2924/173 (2013.01); H01L 2924/17724 (2013.01); H01L 2924/17747 (2013.01);
Abstract
A semiconductor package includes a lower package including a lower substrate, a lower semiconductor chip, and a lower molding layer exposing an upper surface of the lower semiconductor chip, bumps on the lower substrate, the bumps being spaced apart from the lower semiconductor chip, a lead frame on the lower semiconductor chip and on the bumps, the lead frame being electrically connected to the bumps and having a thermal conductivity of about 100 W/mk to about 10,000 W/mk, and an upper package on the lead frame and electrically connected to the lead frame.