The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
May. 31, 2016

Filed:

Aug. 20, 2013
Applicant:

Oracle International Corporation, Redwood City, CA (US);

Inventors:

David Jeffrey, Santa Cruz, CA (US);

Clement Fang, Cupertino, CA (US);

Neil Duncan, Pleasanton, CA (US);

Heechoul Park, San Jose, CA (US);

Lik Cheng, San Jose, CA (US);

Gregory F. Grohoski, Bee Cave, TX (US);

Assignee:

Oracle International Corporation, Redwood Shores, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 12/00 (2006.01); G06F 13/00 (2006.01); G06F 13/28 (2006.01); G11C 7/02 (2006.01); G11C 11/406 (2006.01); G11C 11/408 (2006.01);
U.S. Cl.
CPC ...
G11C 7/02 (2013.01); G11C 11/40611 (2013.01); G11C 11/40622 (2013.01); G11C 11/4085 (2013.01); G11C 11/4087 (2013.01);
Abstract

Embodiments of a row address cache circuit are disclosed that may allow the determination the number of times a row address is used to access a dynamic memory. The row address cache circuit may include a memory, first and second pluralities of counters, and a control circuit. The control circuit may be configured to receive a row address and store the row address in an entry of the memory when the row address has not been previously stored. When the row address has been previously stored in an entry of the memory, the control circuit may be configured to change a value of a counter of the first plurality of counters corresponding the entry. The control circuit may be further configured to change a value of each counter of the second plurality of counters after a pre-determined time interval has elapsed, and initiate a refresh of the dynamic memory.


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