The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
May. 31, 2016
Filed:
Jun. 04, 2014
Fujitsu Limited, Kawasaki-shi, Kanagawa, JP;
William W. Walker, Los Gatos, CA (US);
FUJITSU LIMITED, Kawasaki, JP;
Abstract
A method may include obtaining gate-level circuit design data that describes a gate-level circuit design. The gate-level circuit design data may include one or more instances of each of multiple cells that each may be associated with a corresponding default cell static timing data and a corresponding default cell stress data. The method may include selecting one of the instances of one of the multiple cells, determining in-design stress data associated with the selected instance, and determining whether the in-design stress data is not within a tolerance of the default cell stress data. In response to the in-design stress data not being within the tolerance of the default cell stress data, the method may include generating in-design static timing data describing a timing performance for the selected instance and updating the gate-level circuit design data such that the selected instance is associated with the in-design static timing data.