The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
May. 24, 2016
Filed:
Jan. 18, 2012
Wayne L. Moul, Loveland, CO (US);
Robert J. Behnke, Ii, Erie, CO (US);
Scott E. M. Frushour, Boulder, CO (US);
Jeffrey L. Jensen, Boulder, CO (US);
Wayne L. Moul, Loveland, CO (US);
Robert J. Behnke, II, Erie, CO (US);
Scott E. M. Frushour, Boulder, CO (US);
Jeffrey L. Jensen, Boulder, CO (US);
Covidien LP, Mansfield, MA (US);
Abstract
A method of manufacturing a printed circuit board includes the steps of providing a first layer stack including a first electrically-conductive layer and a first electrically-insulating layer and providing a second layer stack including a second electrically-insulating layer. The first electrically-conductive layer is disposed on the first surface of the first electrically-insulating layer. The second electrically-insulating layer includes one or more electrically-conductive traces disposed on a first surface thereof. The method also includes mounting a device on the first surface of the second electrically-insulating layer such that the device is electrically-coupled to at least one of the one or more electrically-conductive traces, and providing the first layer stack with a cut-out area defining a void that extends from the second surface of the first electrically-insulating layer to the first surface of the first electrically-conductive layer. The cut-out area is configured to receive at least a portion of the device therein.