The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
May. 24, 2016

Filed:

Feb. 03, 2015
Applicant:

Canon Kabushiki Kaisha, Tokyo, JP;

Inventors:

Hirofumi Totsuka, Fujisawa, JP;

Daisuke Yoshida, Ebina, JP;

Shinichi Yamashita, Hachioji, JP;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H04N 5/369 (2011.01); H04N 5/378 (2011.01); H04N 9/04 (2006.01); H04N 5/357 (2011.01); H04N 5/3745 (2011.01); H03M 1/00 (2006.01); H04N 1/00 (2006.01);
U.S. Cl.
CPC ...
H04N 9/045 (2013.01); H03M 1/00 (2013.01); H04N 5/3575 (2013.01); H04N 5/3696 (2013.01); H04N 5/378 (2013.01); H04N 5/3745 (2013.01); H04N 1/00554 (2013.01);
Abstract

A solid-state imaging apparatus, including a plurality of pixels, and an A/D conversion unit configured to convert a pixel signal of an analog signal into a digital signal, wherein the A/D conversion unit comprises a comparator, a sampling unit, a counter, and an output unit configured to output the digital signal based on a count result of the counter and a sampling result of the sampling unit, and the sampling unit comprises first and second latch units configured to latch an output from the comparator in response to first and second clock signals, respectively, and a third latch unit configured to latch an output from the first latch unit in response to an output of the second latch unit.


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