The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
May. 24, 2016

Filed:

Apr. 17, 2013
Applicant:

Semiconductor Components Industries, Llc, Phoenix, AZ (US);

Inventors:

Brian Keelan, Boulder Creek, CA (US);

Dhandapani Dharumalingam, Fremont, CA (US);

Assignee:
Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
H04N 5/369 (2011.01); H01L 27/146 (2006.01); H04N 5/3745 (2011.01);
U.S. Cl.
CPC ...
H04N 5/369 (2013.01); H01L 27/14634 (2013.01); H01L 27/14636 (2013.01); H01L 27/14638 (2013.01); H04N 5/3745 (2013.01);
Abstract

Imaging systems may be provided with stacked-chip image sensors. A stacked-chip image sensor may include a vertical chip stack that includes an array of image pixels and processing circuitry. The image pixel array may be coupled to the processing circuitry through an array of vertical metal interconnects. The image pixel array may be partitioned into image pixel sub-arrays configured to capture image data at a capture frame rate. The processing circuitry may compress image data associated with each image pixel sub-array in parallel and may output the compressed image data to off-chip image processing circuitry at an output frame rate that is less than the capture frame rate. The processing circuitry may determine respective compression block sizes for each image pixel sub-array with which to compress the associated image data and may determine respective output frame rates for image data from each image pixel sub-array.


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