The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
May. 24, 2016

Filed:

Sep. 15, 2014
Applicant:

Thomas & Betts International, Llc, Wilmington, DE (US);

Inventor:

Justin Walraven, San Diego, CA (US);

Assignee:

Thomas & Betts International, LLC, Wilmington, DE (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H03L 7/00 (2006.01); H03L 7/08 (2006.01); H03L 7/095 (2006.01); H02J 9/06 (2006.01); H03L 7/07 (2006.01);
U.S. Cl.
CPC ...
H03L 7/0805 (2013.01); H02J 9/062 (2013.01); H03L 7/07 (2013.01); H03L 7/095 (2013.01); H02J 2009/068 (2013.01); H03L 2207/14 (2013.01);
Abstract

A system includes a first phase-locked loop (PLL) circuit, a slew rate limiter and a second PLL. The first PLL is configured to receive an input signal, generate a first output identifying a frequency associated with the input signal, and generate a second output identifying phase information associated with the input signal. The slew rate limiter is configured to receive the first output from the first PLL, determine whether the frequency of the first output is changing at greater than a predetermined rate, and generate a first signal indicating whether the frequency is changing at greater than the predetermined rate. The second PLL is configured to receive the first signal from the slew rate limiter, receive the second output from the first PLL, and generate an output signal identifying an angle or phase information based on the first signal and the second output.


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