The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
May. 24, 2016
Filed:
Nov. 30, 2015
Renesas Electronics Corporation, Koutou-ku, Tokyo, JP;
Kazuyuki Ito, Kanagawa, JP;
Hiroshi Shirota, Kanagawa, JP;
Renesas Electronics Corporation, Tokyo, JP;
Abstract
If an exclusive OR circuit itself, a component of a signal delay detecting circuit, has failed to operate properly, a signal delay cannot be detected accurately. A malfunction pre-detecting circuitincludes a delay circuit DL to delay input data that is input in parallel to a data input terminal of a flip-flop FFprovided in a subsequent stage of a flip-flop FF, a flip-flop FFT that receives output of the delay circuit DL, and a comparator CMP that compares output of the flip-flop FFand output of the flip-flop FFT. Test data tvand test data tvare input to the malfunction pre-detecting circuitin an operation test mode for testing operation of the malfunction pre-detecting circuit. The test data tvis input to the delay circuit DL. The comparator CMP compares the test data tvand output of the flip-flop FFT in the operation test mode.