The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
May. 24, 2016

Filed:

Feb. 04, 2014
Applicant:

Cypress Semiconductor Corporation, San Jose, CA (US);

Inventors:

Sagy Charel Levy, Zichron Yaakov, IL;

Krishnaswamy Ramkumar, San Jose, CA (US);

Frederick B. Jenne, Mountain House, CA (US);

Sam G Geha, Cupertino, CA (US);

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 29/51 (2006.01); C23C 16/02 (2006.01); C23C 16/30 (2006.01); G11C 16/04 (2006.01); H01L 21/28 (2006.01); H01L 21/314 (2006.01); H01L 29/66 (2006.01); H01L 29/792 (2006.01); H01L 21/02 (2006.01); H01L 29/78 (2006.01);
U.S. Cl.
CPC ...
H01L 29/512 (2013.01); C23C 16/0272 (2013.01); C23C 16/308 (2013.01); G11C 16/0466 (2013.01); H01L 21/0214 (2013.01); H01L 21/02271 (2013.01); H01L 21/28282 (2013.01); H01L 21/3145 (2013.01); H01L 29/518 (2013.01); H01L 29/66833 (2013.01); H01L 29/792 (2013.01); H01L 29/7833 (2013.01);
Abstract

A method of fabricating a memory device is described. Generally, the method includes: forming a tunneling layer on a substrate; forming on the tunneling layer a multi-layer charge storing layer including at least a first charge storing layer comprising an oxygen-rich oxynitride overlying the tunneling layer, and a second charge storing layer overlying the first charge storing layer comprising a silicon-rich and nitrogen-rich oxynitride layer that is oxygen-lean relative to the first charge storing layer and comprises a majority of charge traps distributed in the multi-layer charge storing layer; and forming a blocking layer on the second oxynitride layer; and forming a gate layer on the blocking layer. Other embodiments are also described.


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