The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
May. 24, 2016

Filed:

Dec. 07, 2015
Applicant:

Renesas Electronics Corporation, Tokyo, JP;

Inventor:

Yoshiharu Kaneda, Tokyo, JP;

Assignee:

RENESAS ELECTRONICS CORPORATION, Kawasaki-Shi, Kanagawa, JP;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 23/495 (2006.01); H01L 23/00 (2006.01);
U.S. Cl.
CPC ...
H01L 23/49503 (2013.01); H01L 23/49541 (2013.01); H01L 24/83 (2013.01); H01L 24/85 (2013.01); H01L 24/92 (2013.01); H01L 2224/32245 (2013.01); H01L 2224/48175 (2013.01); H01L 2224/85439 (2013.01); H01L 2224/85455 (2013.01); H01L 2224/92247 (2013.01);
Abstract

A method of manufacturing a semiconductor device includes preparing a lead frame provided with a die pad having an upper surface and a plurality of leads being arranged so as to be aligned on a side of the die pad and each including a wire joint part at a distal end on the side of the die pad, after the preparing the lead frame, mounting a semiconductor chip having a main surface and a plurality of electrode pads formed on the main surface, on the upper surface of the die pad, and after the mounting the semiconductor chip, electrically connecting a first electrode pad among the plurality of electrode pads of the semiconductor chip and a first lead among the plurality of leads to each other via a first wire.


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