The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
May. 24, 2016
Filed:
Mar. 27, 2014
Applicant:
Ps4 Luxco S.a.r.l., Luxembourg, LU;
Inventors:
Vincenzo Ferragina, San Genesio ed Uniti, IT;
Stefano Surico, Bussero, IT;
Giuseppe Moioli, Albino, IT;
Simone Bartoli, Mandello del Lario, IT;
Assignee:
PS4 Luxco S.a.r.l., Luxembourg, LU;
Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G11C 16/34 (2006.01); G11C 16/16 (2006.01); G11C 16/04 (2006.01);
U.S. Cl.
CPC ...
G11C 16/3445 (2013.01); G11C 16/16 (2013.01); G11C 16/3418 (2013.01); G11C 16/0483 (2013.01);
Abstract
Disclosed herein is a method that comprises applying a first voltage to a memory cell, applying again the first voltage to the memory cell when the memory cell have not been shifted to an erased condition, and applying a second voltage to the memory cell when the memory cell have not still been shifted to an erased condition, the second voltage being higher than the first voltage.
Ferragina, Vincenzo. (2016). Erase techniques and circuits therefor for non-volatile memory devices (U.S. Patent No. 9349480). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/9349480
Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile