The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
May. 24, 2016
Filed:
Dec. 19, 2012
Nvidia Corporation, Santa Clara, CA (US);
Brian Fahs, Los Angeles, CA (US);
Eric T. Anderson, Palo Alto, CA (US);
Nick Barrow-Williams, San Francisco, CA (US);
Shirish Gadre, Fremont, CA (US);
Joel James McCormack, Boulder, CO (US);
Bryon S. Nordquist, Santa Clara, CA (US);
Nirmal Raj Saxena, Los Altos Hills, CA (US);
Lacky V. Shah, Los Altos Hills, CA (US);
NVIDIA Corporation, Santa Clara, CA (US);
Abstract
A tag unit configured to manage a cache unit includes a coalescer that implements a set hashing function. The set hashing function maps a virtual address to a particular content-addressable memory unit (CAM). The coalescer implements the set hashing function by splitting the virtual address into upper, middle, and lower portions. The upper portion is further divided into even-indexed bits and odd-indexed bits. The even-indexed bits are reduced to a single bit using a XOR tree, and the odd-indexed are reduced in like fashion. Those single bits are combined with the middle portion of the virtual address to provide a CAM number that identifies a particular CAM. The identified CAM is queried to determine the presence of a tag portion of the virtual address, indicating a cache hit or cache miss.