The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
May. 24, 2016
Filed:
Aug. 21, 2014
Applicant:
Samsung Electronics Co., Ltd., Suwon-si, KR;
Inventors:
Jun Hee Yoo, Gyeonggi-do, KR;
Sung Hyun Lee, Gyeonggi-do, KR;
Dongsoo Kang, Gyeonggi-do, KR;
Sua Kim, Gyeonggi-do, KR;
Haksoo Yu, Gyeonggi-do, KR;
Jaeyoun Youn, Seoul, KR;
Hyojin Choi, Gyeonggi-do, KR;
Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 11/10 (2006.01); G06F 11/00 (2006.01); G11C 8/06 (2006.01); G11C 11/401 (2006.01); G11C 29/44 (2006.01);
U.S. Cl.
CPC ...
G06F 11/00 (2013.01); G11C 8/06 (2013.01); G11C 11/401 (2013.01); G11C 2029/4402 (2013.01);
Abstract
A bad page management system is provided to guarantee a yield of a volatile semiconductor memory device such as a DRAM. A bad page list exists in a DRAM. A page remapper in a memory controller performs a page remapping operation in parallel with a normal operation of a scheduling unit to perform a latency overhead hidden function. A chip size of the DRAM is reduced or minimized. A DRAM controller performs a latency overhead hidden function to control a DRAM.