The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
May. 24, 2016
Filed:
Jun. 08, 2013
Applicant:
Xockets Ip, Llc, Wilmington, DE (US);
Inventors:
Parin Bhadrik Dalal, Milpitas, CA (US);
Stephen Paul Belair, Santa Cruz, CA (US);
Assignee:
Xockets, Inc., San Jose, CA (US);
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 13/36 (2006.01); G06F 9/46 (2006.01); H04L 12/801 (2013.01); G06F 13/16 (2006.01); G06F 9/48 (2006.01); G06F 12/08 (2016.01); G06F 13/362 (2006.01); H04L 12/875 (2013.01); H04L 12/863 (2013.01); H04L 12/861 (2013.01); H04L 12/851 (2013.01);
U.S. Cl.
CPC ...
G06F 9/461 (2013.01); G06F 9/4843 (2013.01); G06F 12/0815 (2013.01); G06F 12/0875 (2013.01); G06F 13/16 (2013.01); G06F 13/362 (2013.01); H04L 47/193 (2013.01); H04L 47/2441 (2013.01); H04L 47/56 (2013.01); H04L 47/624 (2013.01); H04L 47/6295 (2013.01); H04L 49/90 (2013.01);
Abstract
A system can include a host processor connected to memory via a system memory bus; and at least one offload processor module, including at least one offload processor mounted on the offload processor module, and configured to execute operations on data received over the system memory bus, and to output context data to memory, and read context data from the memory, and hardware scheduling logic mounted on the module and configured to control operations of the at least one offload processor.