The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
May. 24, 2016

Filed:

Dec. 13, 2013
Applicant:

Qualcomm Incorporated, San Diego, CA (US);

Inventors:

Binglong Xie, San Diego, CA (US);

Shuxue Quan, San Diego, CA (US);

Ning Bi, San Diego, CA (US);

Jianfeng Ren, San Diego, CA (US);

Lei Xu, San Diego, CA (US);

Ananthapadmanabhan Arasanipalai Kandhadai, San Diego, CA (US);

Assignee:

QUALCOMM Incorporated, San Diego, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 9/44 (2006.01); G06F 9/50 (2006.01); G06F 9/45 (2006.01);
U.S. Cl.
CPC ...
G06F 8/34 (2013.01); G06F 8/451 (2013.01); G06F 9/50 (2013.01); G06F 9/5044 (2013.01); Y02B 60/142 (2013.01);
Abstract

A method includes accessing, at a computing device, data descriptive of a graph representing a program. The graph includes multiple nodes representing execution steps of the program and includes multiple edges representing data transfer steps. The method also includes determining at least two heterogeneous hardware resources of the computing device that are available to execute code represented by one or more of the nodes, and determining one or more paths from a source node to a sink node based on a topology of the graph. The method further includes scheduling execution of code at the at least two heterogeneous hardware resources. The code is represented by at least one of the multiple nodes, and the execution of the code is scheduled based on the one or more paths.


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