Acquisition device with multistage digital equalization

Abstract

An acquisition device includes an analog to digital converter (ADC) composed of multiple interleaved ADCs (sub-ADCs), which receives an analog signal which is converted to digital form. The digitized signal is processed seriatim by a pre-(or trigger-) equalizer, an acquisition memory and a post-(or memory) equalizer. In a calibration mode, frequency responses of the respective sub-ADCs are determined and trigger coefficients are determined for application to the trigger equalizer to effect a preliminary equalization of the digitized signal sufficient to permit operation of the trigger processor in an acquisition mode. Memory coefficients are determined based on residual frequency responses of the sub-ADCs, for application to the memory equalizer. A trigger processor is responsive to the trigger equalizer to select a subset of samples of the digitized signal for loading to the acquisition memory. The trigger equalizer and a memory equalizer are configured for consecutive operation so that, in an acquisition mode, the memory equalizer receives as its input, a digitized signal from the ADC that has been pre-processed in the trigger equalizer, and the memory equalizer corrects only the residue of misalignments and frequency distortions that remain after the trigger equalizer operation.