The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
May. 17, 2016
Filed:
Mar. 25, 2015
Applicant:
Pmc-sierra Us, Inc., Sunnyvale, CA (US);
Inventor:
Tomas A. Dusatko, Vancouver, CA;
Assignee:
MICROSEMI STORAGE SOLUTIONS (U.S.), INC., Aliso Viejo, CA (US);
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H03L 7/085 (2006.01); H03L 7/197 (2006.01); H04L 7/033 (2006.01); H03M 7/30 (2006.01);
U.S. Cl.
CPC ...
H04L 7/0331 (2013.01); H03L 7/085 (2013.01); H03L 7/197 (2013.01); H03M 7/3015 (2013.01);
Abstract
A hybrid analog-digital, dual path, delta-sigma modulator (DSM) based fractional-N phase-lock-loop (PLL) that includes an integral path and a proportional path is provided. The integral path is implemented in the digital domain. The proportional path may be implemented in either the digital or analog domain. A feed-forward error correction signal generator is used to generate a feed-forward signal for attenuating in-band spurs generated by the quantization error of the integral path phase detector.