The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
May. 17, 2016

Filed:

Nov. 13, 2015
Applicant:

S9estre, Llc, Amesbury, MA (US);

Inventor:

Bernd Schafferer, Amesbury, MA (US);

Assignee:

S9ESTRE, LLC, Amesbury, MA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H03M 1/06 (2006.01); H03M 1/10 (2006.01); H03M 3/00 (2006.01); H03M 1/68 (2006.01); H03M 1/00 (2006.01);
U.S. Cl.
CPC ...
H03M 1/066 (2013.01); H03M 1/0658 (2013.01); H03M 1/1014 (2013.01); H03M 1/68 (2013.01); H03M 3/32 (2013.01); H03M 3/384 (2013.01); H03M 3/50 (2013.01); H03M 3/51 (2013.01); H03M 1/002 (2013.01);
Abstract

Methods and devices for the calibration of digital to analog converters (DAC) and analog to digital converters (ADC) are disclosed. In a first step the DAC is calibrated and in a second step the calibrated DAC is used to calibrate the ADC. Averaging techniques and/or equation based techniques are used to further improve the calibration of both components in an iterative process. Embodiments of the invention allow for a very compact physical implementations of the converter. The invention reduces of analog circuitry in favor of digital circuits. Embodiments of the invention are suitable for the implementation in fine line CMOS processes and can operate in a low supply voltage environment.


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