The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
May. 17, 2016

Filed:

Nov. 24, 2014
Applicant:

Advanced Micro Devices, Inc., Sunnyvale, CA (US);

Inventors:

Nuwan S. Jayasena, Sunnyvale, CA (US);

Michael J. Schulte, Austin, TX (US);

Gabriel H. Loh, Bellevue, WA (US);

Michael Ignatowski, Austin, TX (US);

Assignee:

Advanced Micro Devices, Inc., Sunnyvale, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H03K 19/177 (2006.01); G11C 7/00 (2006.01); G06F 15/78 (2006.01); G06F 13/16 (2006.01); G06F 11/10 (2006.01); G06F 13/42 (2006.01); G11C 7/10 (2006.01); G11C 29/00 (2006.01);
U.S. Cl.
CPC ...
H03K 19/1776 (2013.01); G06F 11/1004 (2013.01); G06F 13/1668 (2013.01); G06F 13/4234 (2013.01); G06F 15/7867 (2013.01); G11C 7/1006 (2013.01); G11C 7/1048 (2013.01); G11C 29/70 (2013.01); H03K 19/17776 (2013.01);
Abstract

A die-stacked memory device incorporates a reconfigurable logic device to provide implementation flexibility in performing various data manipulation operations and other memory operations that use data stored in the die-stacked memory device or that result in data that is to be stored in the die-stacked memory device. One or more configuration files representing corresponding logic configurations for the reconfigurable logic device can be stored in a configuration store at the die-stacked memory device, and a configuration controller can program a reconfigurable logic fabric of the reconfigurable logic device using a selected one of the configuration files. Due to the integration of the logic dies and the memory dies, the reconfigurable logic device can perform various data manipulation operations with higher bandwidth and lower latency and power consumption compared to devices external to the die-stacked memory device.


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