The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
May. 17, 2016

Filed:

Jun. 11, 2015
Applicant:

Nichia Corporation, Anan-shi, Tokushima, JP;

Inventors:

Hidetsugu Sumitomo, Anan, JP;

Hisashi Kasai, Tokushima, JP;

Assignee:

NICHIA CORPORATION, Anan-Shi, JP;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/00 (2006.01); H01L 33/00 (2010.01); H01L 33/36 (2010.01); H01L 33/46 (2010.01);
U.S. Cl.
CPC ...
H01L 33/0079 (2013.01); H01L 33/0075 (2013.01); H01L 33/36 (2013.01); H01L 33/46 (2013.01); H01L 2933/0016 (2013.01); H01L 2933/0025 (2013.01); H01L 2933/0033 (2013.01);
Abstract

A method of producing light emitting elements includes providing a wafer that includes a growth substrate and a semiconductor structure formed on the growth substrate, a lower side of the wafer being a growth substrate side, and an upper side of the wafer being a semiconductor structure side as an upper side; forming a separation groove in the wafer from the upper side of the wafer to demarcate portions of the semiconductor structure, the separation groove extending in a depth direction to a location in the wafer; forming a p-electrode and an n-electrode on an upper side of each of the demarcated portions of the semiconductor structure; forming a dielectric multilayer film at an upper side of the wafer, including portions defining the separation groove, by using an atomic layer deposition method; and separating the wafer into a plurality of light emitting elements by removing a portion of the wafer from a lower side of the wafer to at least the location to which the separation groove extends.


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