The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
May. 17, 2016

Filed:

Mar. 26, 2015
Applicant:

Texas Instruments Incorporated, Dallas, TX (US);

Inventors:

Xiangzheng Bo, Plano, TX (US);

Douglas Tad Grider, McKinney, TX (US);

Assignee:
Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
G11C 16/04 (2006.01); H01L 27/115 (2006.01); G11C 16/26 (2006.01); H01L 29/423 (2006.01); H01L 29/788 (2006.01); H01L 29/49 (2006.01); H01L 21/66 (2006.01); H01L 21/265 (2006.01); H01L 21/285 (2006.01); H01L 29/45 (2006.01);
U.S. Cl.
CPC ...
H01L 27/11521 (2013.01); G11C 16/0441 (2013.01); G11C 16/26 (2013.01); H01L 21/26586 (2013.01); H01L 21/28518 (2013.01); H01L 22/20 (2013.01); H01L 29/42328 (2013.01); H01L 29/45 (2013.01); H01L 29/495 (2013.01); H01L 29/4916 (2013.01); H01L 29/4966 (2013.01); H01L 29/7883 (2013.01);
Abstract

A split-gate flash memory cell (cell) includes a semiconductor surface. A first control gate (CG) on a first floating gate (FG) and a second CG on a second floating gate (FG) are on the semiconductor surface. A common source or common drain is between the first and second FG. A first select gate and a second select gate on a select gate dielectric layer is between a first BL source or drain (S/D) and the first FG and between a second BL S/D and the second FG, respectively. The first select gate has a first pocket region that has a first doping distribution different from a second doping distribution in a second pocket region associated with the second select gate which reduces a variation in read current (Ir) for the cell between measuring Ir using the first select gate and measuring Ir using the second select gate.


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