The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
May. 17, 2016
Filed:
Sep. 29, 2009
Tom Zhong, Saratoga, CA (US);
Adam Zhong, Milpitas, CA (US);
Wai-ming J. Kan, San Ramon, CA (US);
Chyu-jiuh Torng, Pleasanton, CA (US);
Tom Zhong, Saratoga, CA (US);
Adam Zhong, Milpitas, CA (US);
Wai-Ming J. Kan, San Ramon, CA (US);
Chyu-Jiuh Torng, Pleasanton, CA (US);
Headway Technologies, Inc., Milpitas, CA (US);
Abstract
The structure and method of formation of an integrated CMOS level and active device level that can be a memory device level. The integration includes the formation of a 'super-flat' interface between the two levels formed by the patterning of a full complement of active and dummy interconnecting vias using two separate patterning and etch processes. The active vias connect memory devices in the upper device level to connecting pads in the lower CMOS level. The dummy vias may extend up to an etch stop layer formed over the CMOS layer or may be stopped at an intermediate etch stop layer formed within the device level. The dummy vias thereby contact memory devices but do not connect them to active elements in the CMOS level.