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The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Patent No.:

US 9343460 B1

PDFFull Text
Date of Patent:
May. 17, 2016

Filed:

Jun. 22, 2015

Semiconductor device with output circuit and pad arrangements

Applicant:

Renesas Electronics Corporation, Kawasaki-shi, Kanagawa, JP;

Inventors:

Takahiro Hayashi, Tokyo, JP;

Shunsuke Toyoshima, Tokyo, JP;

Kazuo Sakamoto, Tokyo, JP;

Naozumi Morino, Tokyo, JP;

Kazuo Tanaka, Tokyo, JP;

Assignee:

Renesas Electronics Corporation, Tokyo, JP;

Attorney:

Shapiro, Gabor and Rosenberger, PLLC

Primary Examiner:

Selim Ahmed

Int. Cl.
CPC ...
H01L 29/74 (2006.01); H01L 27/092 (2006.01); H01L 23/528 (2006.01); H01L 23/58 (2006.01); H01L 23/00 (2006.01); H01L 27/02 (2006.01); H01L 23/498 (2006.01); H01L 23/532 (2006.01); H01L 23/522 (2006.01);
U.S. Cl.
CPC ...
H01L 27/092 (2013.01); H01L 23/49811 (2013.01); H01L 23/5286 (2013.01); H01L 23/53228 (2013.01); H01L 23/585 (2013.01); H01L 24/05 (2013.01); H01L 24/06 (2013.01); H01L 24/49 (2013.01); H01L 27/0255 (2013.01); H01L 23/5226 (2013.01); H01L 2224/02166 (2013.01); H01L 2224/05025 (2013.01); H01L 2224/05093 (2013.01); H01L 2224/05095 (2013.01); H01L 2224/05124 (2013.01); H01L 2224/05624 (2013.01); H01L 2224/06102 (2013.01); H01L 2224/06133 (2013.01); H01L 2224/06143 (2013.01); H01L 2224/06153 (2013.01); H01L 2224/06163 (2013.01); H01L 2224/49105 (2013.01); H01L 2224/85399 (2013.01); H01L 2924/00014 (2013.01); H01L 2924/01004 (2013.01); H01L 2924/01005 (2013.01); H01L 2924/01006 (2013.01); H01L 2924/01013 (2013.01); H01L 2924/01014 (2013.01); H01L 2924/01015 (2013.01); H01L 2924/01019 (2013.01); H01L 2924/01029 (2013.01); H01L 2924/01033 (2013.01); H01L 2924/01074 (2013.01); H01L 2924/01082 (2013.01); H01L 2924/12036 (2013.01); H01L 2924/1306 (2013.01); H01L 2924/14 (2013.01);
Abstract

The present invention has for its purpose to provide a technique capable of reducing planar dimension of the semiconductor device. An input/output circuit is formed over the semiconductor substrate, a grounding wiring and a power supply wiring pass over the input/output circuit, and a conductive layer for a bonding pad is formed thereover. The input/output circuit is formed of MISFET elements in the nMISFET forming region and the pMISFET forming region, resistance elements in the resistance element forming regions and diode elements in the diode element forming regions functioning as protective elements. A wiring connected to the protective elements and positioned under the grounding wiring and the power supply wiring is pulled out in a pulling-out region between the nMISFET forming region and the pMISFET forming region and between the grounding wiring and the power supply wiring to be connected to the conductive layer.

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