The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
May. 17, 2016
Filed:
Feb. 14, 2014
Applicant:
Seiko Instruments Inc., Chiba-shi, Chiba, JP;
Inventor:
Tomomitsu Risaki, Chiba, JP;
Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 23/62 (2006.01); H01L 27/02 (2006.01); H01L 23/528 (2006.01); H01L 23/522 (2006.01);
U.S. Cl.
CPC ...
H01L 27/027 (2013.01); H01L 23/528 (2013.01); H01L 23/5228 (2013.01);
Abstract
In order to provide a semiconductor device having a high ESD tolerance, a source wiring () is formed on a gate () and a source () in a region of an NMOS transistor (). The source wiring () electrically connects the gate (), the source (), and a ground terminal. A drain wiring () is formed on a drain () in the region of the NMOS transistor () . The drain wiring () electrically connects the drain () and a pad () serving as an external connection electrode. Moreover, in the region of the NMOS transistor (), the drain wiring () has the same wiring width as the source wiring ().