The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
May. 17, 2016

Filed:

May. 19, 2014
Applicant:

Qualcomm Incorporated, San Diego, CA (US);

Inventors:

Yang Du, Carlsbad, CA (US);

Karim Arabi, San Diego, CA (US);

Assignee:

QUALCOMM Incorporated, San Diego, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 23/48 (2006.01); H01L 21/822 (2006.01); H01L 23/528 (2006.01); H01L 23/522 (2006.01); H01L 21/768 (2006.01); H01L 21/50 (2006.01); H01L 27/06 (2006.01);
U.S. Cl.
CPC ...
H01L 21/8221 (2013.01); H01L 21/50 (2013.01); H01L 21/76895 (2013.01); H01L 23/528 (2013.01); H01L 23/5226 (2013.01); H01L 27/0688 (2013.01); H01L 27/0694 (2013.01); H01L 2224/80006 (2013.01); H01L 2224/80896 (2013.01); H01L 2224/9202 (2013.01);
Abstract

Methods for constructing three dimensional integrated circuits and related systems are disclosed. In one aspect, a first tier is constructed by creating active elements such as transistors on a holding substrate. An interconnection metal layer is created above the active elements. Metal bonding pads are created within the interconnection metal layer. A second tier is also created, either concurrently or sequentially. The second tier is created in much the same manner as the first tier and is then placed on the first tier, such that the respective metal bonding pads align and are bonded one tier to the other. The holding substrate of the second tier is then released. A back side of the second tier is then thinned, such that the back surfaces of the active elements (for example, a back of a gate in a transistor) are exposed. Additional tiers may be added if desired essentially repeating this process.


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