The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
May. 17, 2016

Filed:

Sep. 26, 2013
Applicant:

International Business Machines Corporation, Armonk, NY (US);

Inventors:

John E. Barth, Jr., Williston, VT (US);

Srivatsan Chellappa, Tempe, AZ (US);

Dean L. Lewis, Williston, VT (US);

Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
G06F 12/00 (2006.01); G11C 29/00 (2006.01); G06F 9/445 (2006.01); G06F 9/32 (2006.01); G06F 12/08 (2016.01); G06F 11/10 (2006.01); G06F 12/12 (2016.01); G06F 12/06 (2006.01); G06F 13/22 (2006.01); G06F 13/38 (2006.01); G06F 12/10 (2016.01); G06F 12/04 (2006.01); G11C 15/00 (2006.01); G11C 8/06 (2006.01);
U.S. Cl.
CPC ...
G11C 29/76 (2013.01); G06F 8/65 (2013.01); G06F 9/328 (2013.01); G06F 11/1008 (2013.01); G06F 12/04 (2013.01); G06F 12/0638 (2013.01); G06F 12/0868 (2013.01); G06F 12/0886 (2013.01); G06F 12/109 (2013.01); G06F 12/1027 (2013.01); G06F 12/126 (2013.01); G06F 13/225 (2013.01); G06F 13/385 (2013.01); G11C 8/06 (2013.01); G11C 15/00 (2013.01);
Abstract

A memory having variable size blocks of failed memory addresses is connected to a TCAM storing data values of ranges of addresses in the memory. The ranges of addresses correspond to virtual addresses that, in combination with an offset, point away from failed memory addresses. A reduction circuit connected to the TCAM produces an output for each programmed range of addresses based on a virtual address. A priority encoder, connected to the reduction circuit, selects a first range from the reduction circuit and passes the first range to a random-access memory (RAM). Responsive to the virtual address bring an address in one of the ranges of addresses, the priority encoder passes the first range containing the virtual address to the RAM, which passes a corresponding offset value to the Adder based on the first range. The Adder calculates a physical memory address directing the virtual address to a functional memory location.


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