The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
May. 17, 2016

Filed:

Jan. 05, 2012
Applicants:

Sarunya Bangsaruntip, Mount Kisco, NY (US);

Guy Cohen, Mohegan Lake, NY (US);

Amlan Majumdar, White Plains, NY (US);

Jeffrey W. Sleight, Ridgefield, CT (US);

Inventors:

Sarunya Bangsaruntip, Mount Kisco, NY (US);

Guy Cohen, Mohegan Lake, NY (US);

Amlan Majumdar, White Plains, NY (US);

Jeffrey W. Sleight, Ridgefield, CT (US);

Assignee:

GlobalFoundries Inc., Ugland House, KY;

Attorneys:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 29/66 (2006.01); H01L 29/788 (2006.01); G11C 11/56 (2006.01); H01L 21/28 (2006.01); H01L 29/423 (2006.01); H01L 29/06 (2006.01);
U.S. Cl.
CPC ...
G11C 11/5671 (2013.01); H01L 21/28273 (2013.01); H01L 29/0673 (2013.01); H01L 29/42332 (2013.01); H01L 29/42336 (2013.01); H01L 29/66825 (2013.01); H01L 29/7881 (2013.01);
Abstract

A floating gate transistor, memory cell, and method of fabricating a device. The floating gate transistor includes one or more gated wires substantially cylindrical in form. The floating gate transistor includes a first gate dielectric layer at least partially covering the gated wires. The floating gate transistor further includes a plurality of gate crystals discontinuously arranged upon the first gate dielectric layer. The floating gate transistor also includes a second gate dielectric layer covering the plurality of gate crystals and the first gate dielectric layer.


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