The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
May. 17, 2016

Filed:

Mar. 12, 2015
Applicant:

Panasonic Intellectual Property Management Co., Ltd., Osaka, JP;

Inventors:

Takanori Ueda, Kanagawa, JP;

Kazuyuki Kouno, Osaka, JP;

Yasuo Murakuki, Kyoto, JP;

Masayoshi Nakayama, Kyoto, JP;

Yuriko Ishitobi, Osaka, JP;

Keita Takahashi, Nara, JP;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G11C 16/04 (2006.01); G11C 5/08 (2006.01); G11C 11/56 (2006.01); G11C 11/18 (2006.01); G11C 11/14 (2006.01); G11C 11/15 (2006.01); G11C 13/00 (2006.01); G11C 11/16 (2006.01); G11C 7/14 (2006.01);
U.S. Cl.
CPC ...
G11C 5/08 (2013.01); G11C 7/14 (2013.01); G11C 11/14 (2013.01); G11C 11/15 (2013.01); G11C 11/16 (2013.01); G11C 11/18 (2013.01); G11C 11/5607 (2013.01); G11C 13/004 (2013.01); G11C 13/0004 (2013.01); G11C 2013/0054 (2013.01); G11C 2213/79 (2013.01);
Abstract

A memory array includes a resistive memory cell array having a first cell transistor and a resistance change element connected in series and a reference cell array having a second cell transistor and a resistance element connected in series. The second cell transistor of the reference cell array is connected to a reference source line, and the resistance element is connected to a reference bit line. A dummy memory cell is connected to the reference bit line in the memory cell array, and both ends of a resistance change element of the dummy memory cell are short-circuited through the reference bit line.


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