The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
May. 17, 2016

Filed:

Apr. 15, 2009
Applicants:

Dong-hyeon Ki, Cheonan-si, KR;

Ho-kyoon Kwon, Seoul, KR;

Ju-hee Lee, Cheonan-si, KR;

Byoung-sun NA, Hwaseong-si, KR;

Inventors:

Dong-Hyeon Ki, Cheonan-si, KR;

Ho-Kyoon Kwon, Seoul, KR;

Ju-Hee Lee, Cheonan-si, KR;

Byoung-Sun Na, Hwaseong-si, KR;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G09G 3/36 (2006.01); G11C 19/18 (2006.01); G11C 19/28 (2006.01);
U.S. Cl.
CPC ...
G09G 3/3677 (2013.01); G11C 19/184 (2013.01); G11C 19/28 (2013.01); G09G 2310/0286 (2013.01);
Abstract

A method of driving a gate line includes: charging one of a scan start signal and a carry signal provided from a previous stage to a first node of a present stage; outputting a gate signal through a gate node of the present stage by pulling up a high level of a first clock signal at the first node to boost up a voltage potential of the first node; discharging the voltage potential of the first node and a voltage potential of the gate node to hold the first node and the gate node at a first power voltage as the first clock signal is shifted to a low level; and receiving a voltage potential signal of a second node of the previous stage, the second node holding a gate signal outputted from the previous stage, to reduce a ripple generated at the first node.


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