The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
May. 17, 2016
Filed:
Aug. 21, 2013
International Business Machines Corporation, Armonk, NY (US);
Wei Fan, New York, NY (US);
Nagui Halim, Yorktown Heights, NY (US);
Mark C. Johnson, South Burlington, VT (US);
Srinivasan Parthasarathy, Yonkers, NY (US);
Deepak S. Turaga, Elmsford, NY (US);
Olivier Verscheure, Hopewell Junction, NY (US);
International Business Machines Corporation, Armonk, NY (US);
Abstract
The present invention describes a method and system for optimizing a test flow within each ATE (Automated Test Equipment) station. The test flow includes a plurality of test blocks. A test block includes a plurality of individual tests. A computing system schedule the test flow based one or more of: a test failure model, test block duration and a yield model. The failure model determines an order or sequence of the test blocks. There are at least two failure models: independent failure model and dependant failure model. The yield model describes whether a semiconductor chip is defective or not. Upon completing the scheduling, the ATE station conducts tests according to the scheduled test flow. The present invention can also be applied to software testing.