The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
May. 17, 2016

Filed:

Jan. 28, 2014
Applicant:

Altera Corporation, San Jose, CA (US);

Inventors:

Yu Ying Ong, Ampang, MY;

Weizhong Xu, Cupertino, CA (US);

Assignee:

Altera Corporation, San Jose, CA (US);

Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
G06F 11/10 (2006.01); G06F 13/16 (2006.01); G06F 3/06 (2006.01); G06F 12/00 (2006.01); G11C 16/10 (2006.01); G11C 16/26 (2006.01); G11C 29/04 (2006.01);
U.S. Cl.
CPC ...
G06F 11/1056 (2013.01); G06F 3/068 (2013.01); G06F 3/0658 (2013.01); G06F 11/10 (2013.01); G06F 11/1048 (2013.01); G06F 12/00 (2013.01); G06F 13/16 (2013.01); G06F 13/1668 (2013.01); G06F 13/1673 (2013.01); G06F 13/1694 (2013.01); G11C 16/10 (2013.01); G11C 16/26 (2013.01); G11C 2029/0411 (2013.01); Y02B 60/1228 (2013.01);
Abstract

A programmable integrated circuit with memory interface circuitry is provided. The memory interface circuitry may include soft memory interface logic and hard memory interface logic. The soft memory interface logic may be implemented using programmable circuits, whereas the hard memory interface logic may be implemented using non-programmable dedicated circuits. The soft memory interface logic may include error correction code (ECC) encoder and decoder circuits and circuitry for carrying out a read modified write (RMW) operation. The hard memory interface logic may include a write data buffer, a read data buffer, and other circuitry for supporting the RMW operation. The soft memory interface logic is interposed between the hard memory interface logic and the user logic on the programmable integrated circuit.


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