The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
May. 10, 2016

Filed:

Dec. 06, 2013
Applicant:

Olympus Corporation, Tokyo, JP;

Inventors:

Yosuke Kusano, Tokyo, JP;

Susumu Yamazaki, Tokyo, JP;

Assignee:

OLYMPUS CORPORATION, Tokyo, JP;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H03K 17/78 (2006.01); H01L 27/00 (2006.01); H04N 5/378 (2011.01); H01L 27/146 (2006.01); H04N 5/376 (2011.01); H03M 1/06 (2006.01); H03M 1/12 (2006.01); H03M 1/56 (2006.01);
U.S. Cl.
CPC ...
H04N 5/378 (2013.01); H01L 27/146 (2013.01); H03M 1/06 (2013.01); H04N 5/3765 (2013.01); H03M 1/123 (2013.01); H03M 1/56 (2013.01);
Abstract

A solid-state imaging apparatus includes a pixel unit which has a plurality of pixels disposed in a two-dimensional matrix shape, wherein each of the pixels that a photoelectrical conversion element which generates a photoelectrical conversion signal corresponding to an amount of incident light disposed on a first substrate, and which outputs a photoelectrical conversion signal generated by each of the pixels to each row as a pixel signal, and an analog-to-digital converter which is disposed on every one or more columns of the pixel unit and generates a digital signal by digitizing a phase state of a multi-phase clock including clock signals of a plurality of phases different from each other at predetermined fixed intervals according to the pixel signal. Each of first and second circuit configuration units whose circuit scales are determined according to the multi-phase clock is disposed on a different substrate of a first or second substrate.


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