The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
May. 10, 2016
Filed:
Nov. 19, 2012
China Electronic Technology Corporation, 24th Research Institute, Chongqing, CN;
Xi Chen, Chongqing, CN;
Gang-Yi Hu, Chongqing, CN;
Xue-Liang Xu, Chongqing, CN;
Xing-Fa Huang, Chongqing, CN;
Liang Li, Chongqing, CN;
Xiao-Feng Shen, Chongqing, CN;
Ming-Yuan Xu, Chongqing, CN;
Lei Zhang, Chongqing, CN;
Yan Wang, Chongqing, CN;
Rong-Ke Ye, Chongqing, CN;
You-Hua Wang, Chongqing, CN;
Xu Huang, Chongqing, CN;
Jiao-Xue Li, Chongqing, CN;
CHINA ELECTRONIC TECHNOLOGY CORPORATION, 24TH RESEARCH INSTITUTE, Chongqing, CN;
Abstract
A high-linearity CMOS input buffer circuit is provided for neutralizing non-linearity of follower circuits' transconductance and output impedance resulting from input signals' variation. In doing so, the linearity of CMOS input buffer is improved. The buffer circuit includes a CMOS input follower circuit, a linearity improvement circuit of follower transistor, a current source load, and a linearity improvement circuit of load impedance. The buffer circuit is fabricated in standard CMOS process, featuring low cost, simplicity and strong linearity at high frequency. It has wide applications in analog and hybrid analog-digital CMOS ICs requiring high linearity input buffer.