The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
May. 10, 2016
Filed:
Aug. 23, 2015
Applicant:
Freescale Semiconductor, Inc., Austin, TX (US);
Inventors:
Krishna Thakur, Noida, IN;
Deependra K. Jain, Noida, IN;
Devesh P. Singh, Uttar Pradesh, IN;
Anand Kumar Sinha, Noida, IN;
Avinash Chandra Tripathi, Noida, IN;
Assignee:
FREESCALE SEMICONDUCTOR, INC., Austin, TX (US);
Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H03L 7/06 (2006.01); H03K 5/134 (2014.01); H03K 3/03 (2006.01); H03K 19/0185 (2006.01); H03L 7/08 (2006.01); H03L 7/099 (2006.01); H03K 5/00 (2006.01);
U.S. Cl.
CPC ...
H03K 5/134 (2014.07); H03K 3/0315 (2013.01); H03K 19/018521 (2013.01); H03L 7/0805 (2013.01); H03L 7/0995 (2013.01); H03K 2005/00019 (2013.01);
Abstract
A buffer circuit includes an inverter and a level-shifter. The inverter receives a first oscillating signal at a first voltage level and generates an inverted version of the first oscillating signal at a second voltage level. The level-shifter receives a second oscillating signal at a third voltage level, which has a phase difference from the first oscillating signal, and the inverted first oscillating signal, and generates a buffer output signal at a fourth voltage level.