The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
May. 10, 2016

Filed:

May. 29, 2014
Applicant:

Hrl Laboratories Llc., Malibu, CA (US);

Inventors:

Rongming Chu, Agoura Hills, CA (US);

Mary Y. Chen, Beverly Hills, CA (US);

Xu Chen, Los Angeles, CA (US);

Zijian “Ray” Li, Oak Park, CA (US);

Karim S. Boutros, Moorpark, CA (US);

Assignee:

HRL Laboratories, LLC, Malibu, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 29/778 (2006.01); H01L 29/78 (2006.01); H01L 29/66 (2006.01); H01L 29/423 (2006.01); H01L 29/51 (2006.01); H01L 29/20 (2006.01);
U.S. Cl.
CPC ...
H01L 29/7827 (2013.01); H01L 29/66462 (2013.01); H01L 29/66522 (2013.01); H01L 29/66666 (2013.01); H01L 29/7783 (2013.01); H01L 29/7786 (2013.01); H01L 29/2003 (2013.01); H01L 29/4236 (2013.01); H01L 29/42376 (2013.01); H01L 29/513 (2013.01);
Abstract

A field-effect transistor (FET) includes a plurality of semiconductor layers, a source electrode and a drain electrode contacting one of the semiconductor layers, a first dielectric layer on a portion of a top semiconductor surface between the source and drain electrodes, a first trench extending through the first dielectric layer and having a bottom located on a top surface or within one of the semiconductor layers, a second dielectric layer lining the first trench and covering a portion of the first dielectric layer, a third dielectric layer over the semiconductor layers, the first dielectric layer, and the second dielectric layer, a second trench extending through the third dielectric layer and having a bottom located in the first trench on the second dielectric layer and extending over a portion of the second dielectric, and a gate electrode filling the second trench.


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