The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
May. 10, 2016

Filed:

Dec. 17, 2013
Applicants:

Boe Technology Group Co., Ltd., Beijing, CN;

Chengdu Boe Optoelectronics Technology Co., Ltd., Chengdu, CN;

Inventors:

Xiaodan Wei, Beijing, CN;

Xiaofeng Yang, Beijing, CN;

Dongkoog Jang, Beijing, CN;

Shuibin Ni, Beijing, CN;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/00 (2006.01); H01L 29/66 (2006.01); H01L 27/12 (2006.01); H01L 21/283 (2006.01); H01L 21/306 (2006.01); H01L 21/308 (2006.01); H01L 21/3213 (2006.01); H01L 21/67 (2006.01); H01L 21/677 (2006.01); H01L 29/786 (2006.01);
U.S. Cl.
CPC ...
H01L 29/66742 (2013.01); H01L 21/283 (2013.01); H01L 21/3081 (2013.01); H01L 21/3086 (2013.01); H01L 21/30604 (2013.01); H01L 21/32133 (2013.01); H01L 21/32139 (2013.01); H01L 21/6723 (2013.01); H01L 21/67069 (2013.01); H01L 21/67075 (2013.01); H01L 21/67109 (2013.01); H01L 21/67161 (2013.01); H01L 21/67207 (2013.01); H01L 21/67742 (2013.01); H01L 27/1288 (2013.01); H01L 29/786 (2013.01);
Abstract

The method for manufacturing the TFT includes: forming a semiconductor film, a doped semiconductor film, a source/drain electrode film, and a first patterned photoresist layer sequentially; performing first etching to remove the source/drain electrode film on a region that is not covered by the first patterned photoresist layer; performing second etching to remove the doped semiconductor film and the semiconductor film on a region that is not covered by the first patterned photoresist layer; performing ashing treatment on the photoresist layer to remove the photoresist layer on the channel region; hard-baking the photoresist layer after the ashing treatment; performing third etching to remove the source/drain electrode film on a region that is not covered by the photoresist layer; and performing fourth etching to remove the doped semiconductor film on the region that is not covered by the photoresist layer.


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