The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
May. 10, 2016
Filed:
Nov. 13, 2012
General Electric Company, Schenectady, NY (US);
Eladio Clemente Delgado, Burnt Hills, NY (US);
John Stanley Glaser, Niskayuna, NY (US);
Brian Lynn Rowden, Ballston Lake, NY (US);
General Electric Company, Schenectady, NY (US);
Abstract
A surface mount package includes at least one semiconductor device and a POL packaging and interconnect system formed about the at least one semiconductor device that is configured enable mounting of the surface mount package to an external circuit. The POL system includes a dielectric layer overlying a first surface of the semiconductor device(s) and a metal interconnect structure extending through vias formed through the dielectric layer so as to be electrically coupled to connection pads on the semiconductor device(s). A metallization layer is formed over the metal interconnect structure that comprises a flat planar structure, and a double-sided ceramic substrate is positioned on a second surface of the semiconductor device(s), with the double-sided ceramic substrate being configured to electrically isolate a drain of the semiconductor device(s) from an external circuit when the surface mount package is joined thereto and to conduct heat away from the semiconductor device(s).