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The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Patent No.:

US 9337147 B1

PDFFull Text
Date of Patent:
May. 10, 2016

Filed:

Jun. 19, 2015

Semiconductor device and a method of manufacturing the same and designing the same

Applicant:

Renesas Electronics Corporation, Kanagawa, JP;

Inventors:

Kenichi Kuroda, Tachikawa, JP;

Kozo Watanabe, Kokubunji, JP;

Hirohiko Yamamoto, Hachioji, JP;

Assignee:

Renesas Electronics Corporation, Kanagawa, JP;

Attorneys:

Gregory E. Montone

Roberts Mlotkowski Safran & Cole P.C.

Primary Examiner:

William Coleman

Int. Cl.
CPC ...
H01L 23/528 (2006.01); H01L 21/3105 (2006.01); H01L 21/762 (2006.01); H01L 23/522 (2006.01); H01L 27/02 (2006.01); H01L 27/118 (2006.01); H01L 29/06 (2006.01); H01L 21/74 (2006.01); H01L 23/532 (2006.01); H01L 29/49 (2006.01);
U.S. Cl.
CPC ...
H01L 23/5283 (2013.01); H01L 21/31053 (2013.01); H01L 21/74 (2013.01); H01L 21/76224 (2013.01); H01L 21/76229 (2013.01); H01L 23/522 (2013.01); H01L 23/53228 (2013.01); H01L 27/0207 (2013.01); H01L 27/11807 (2013.01); H01L 29/0649 (2013.01); H01L 29/0653 (2013.01); H01L 29/0692 (2013.01); H01L 29/4925 (2013.01); H01L 23/528 (2013.01); H01L 2924/0002 (2013.01);
Abstract

A semiconductor device includes grooves defining an active region, including a MISFET, and dummy regions. A first interlayer insulation film is formed over the MISFET, the active region and the dummy regions. A first wiring, and first and second dummy wirings are formed over the first interlayer insulation film. A second interlayer insulation film is formed over the first wiring and the dummy wirings. The second dummy wirings are arranged between the first wiring and the first dummy wirings, and the pitch of the first dummy wirings is larger than that of the second dummy wirings. In planar view, the first and second dummy wirings are arranged over the dummy regions, and the size of each of the first dummy wirings is larger than size of each of the second dummy wirings. The first wiring and the first and second dummy wirings are formed of copper as a major component.

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